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When will the first 'next gen' console arrive?

  • H2 2019

    Votes: 638 14.1%
  • H1 2020

    Votes: 724 16.0%
  • H2 2020

    Votes: 2,813 62.2%
  • H1 2021

    Votes: 141 3.1%
  • H2 2021

    Votes: 208 4.6%

  • Total voters
    4,524
  • Poll closed .
Nov 12, 2017
2,877
Post in the correct thread....

Re: PS5 BC, is it a possibility at all that it could have a 7nm PS4 APU in it instead of being engineered into the PS5 APU? Maybe it could also be re-purposed as the PS1 chipset was in PS2 too?

ETA: Wait....The MS event isn't being livestreamed? If true then I don't see anything big HW wise.
Yes it will be (the one with Phil)
 

Carn

Member
Oct 27, 2017
11,911
The Netherlands
Post in the correct thread....

Re: PS5 BC, is it a possibility at all that it could have a 7nm PS4 APU in it instead of being engineered into the PS5 APU? Maybe it could also be re-purposed as the PS1 chipset was in PS2 too?

I guess it could, but I don't see much sense in that because everything points to a similar architecture as the current generation. Adding the ps1 chip to the ps2 and the ps2s to ps3 has always been a weird bc solution to me, because it doesn't really leverage the new hardware.
 

Deleted member 5764

User requested account closure
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Oct 25, 2017
6,574
Oh sorry...I thought the above linked tweet was a reference to the X018 event. Didn't realise the Surface event was today.

No worries! I'm not sure we have any real leaks or rumors about the X018 event just yet. I've seen speculation but that's about it. Knowing Microsoft, I'm sure that something will get out prior to November though...
 

anexanhume

Member
Oct 25, 2017
12,913
Maryland
Post in the correct thread....

Re: PS5 BC, is it a possibility at all that it could have a 7nm PS4 APU in it instead of being engineered into the PS5 APU? Maybe it could also be re-purposed as the PS1 chipset was in PS2 too?

ETA: Wait....The MS event isn't being livestreamed? If true then I don't see anything big HW wise.
I think the Cerny/Simpson patents show they're trying very hard to not have to have dedicated HW for BC.
 

BitsandBytes

Member
Dec 16, 2017
4,576
I think the Cerny/Simpson patents show they're trying very hard to not have to have dedicated HW for BC.

I have always thought those patents refer only to their work on PS4 Pro (Mark Cerny even said BC was hard to do even within the same system in the DF Pro interview). Also over at B3D it now seems the updates to those patents early this year were just for the name change to SIE? Not because they are necessarily doing the same on PS5. I just worry how much customisation is needed and to what extent it affects PS5 specs. Probably unfounded TBH, but still.


Ah there's an event today? ..ok was a fuckin nothing then )

I think we were both confused!?
 

anexanhume

Member
Oct 25, 2017
12,913
Maryland
I have always thought those patents refer only to their work on PS4 Pro (Mark Cerny even said BC was hard to do even within the same system in the DF Pro interview). Also over at B3D it now seems the updates to those patents early this year were just for the name change to SIE? Not because they are necessarily doing the same on PS5. I just worry how much customisation is needed and to what extent it affects PS5 specs. Probably unfounded TBH, but still.

The language talks about altering cache behavior and outright disabling some features in the CPU. The GPU was architectural enhanced, but the CPU was just a faster Jaguar. They could downclock it and call it a day.

In aspects of the current disclosure, in timing testing mode CPU resources may be configured to be restricted in ways that affect the timing of execution of application code. Queues, e.g., store and load queues, retirement queues, and scheduling queues, may be configured to be reduced in size (e.g., the usable portion of the resource may be restricted). Caches, such as the L1 I-Cache and D-Cache, the ITLB and DTLB cache hierarchies, and higher level caches may be reduced in size (e.g. the number of values that can be stored in a fully associative cache may be reduced, or for a cache with a limited number of ways the available bank count or way count may be reduced). The rate of execution of all instructions or specific instructions running on the ALU, AGU or SIMD pipes may be reduced (e.g. the latency increases and/or the throughput decreases).

In aspects of the current disclosure, in timing testing mode, the application threads may execute on a CPU core different from that designated by the application. By way of example, but not by way of limitation, in an system with two clusters (cluster "A" and cluster "B") each with two cores, all threads designated for execution on core 0 of cluster A could instead by executed on core 0 of cluster B, and all threads designated for execution on core 0of cluster B could instead by executed on core 0 of cluster A, resulting in different timing of execution of thread processing due to sharing the cluster high level cache with different threads than under normal operation of the device.

In addition, other behaviors of one or more caches, such as the L1 I-Cache and D-Cache, the ITLB and DTLB cache hierarchies, and higher level caches may be modified in ways the disrupt timing in the timing testing mode. One non-limiting example of such a change in cache behavior modification would be to change whether a particular cache is exclusive or inclusive. A cache that is inclusive in the normal mode may be configured to be exclusive in the timing testing mode or vice versa.

Another non-limiting example of a cache behavior modification involves cache lookup behavior. In the timing testing mode, cache lookups may be done differently than in the normal mode. Memory access for certain newer processor hardware may actually slow down compared to older hardware if the newer hardware translates from virtual to physical address before a cache lookup and the older hardware does not. For cache entries stored by physical address, as is commonly done for multi-core CPU caches 325, a virtual address is always translated to a physical address before performing a cache look up (e.g., in L1 and L2). Always translating a virtual address to a physical address before performing any cache lookup allows a core that writes to a particular memory location to notify other cores not to write to that location. By contrast, cache lookups for cache entries stored according to virtual address (e.g., for GPU caches 334) can be performed without having to translate the address. This is faster because address translation only needs to be performed in the event of a cache miss, i.e., an entry is not in the cache and must be looked up in memory 340. The difference in cache behavior between may introduce a delay of 5 to 1000 cycles in newer hardware, e.g., if older GPU hardware stores cache entries by virtual address and newer GPU hardware stores cache entries by physical address. To test the application 322 for errors resulting from differences in cache lookup behavior, in the timing testing mode, caching and cache lookup behavior for one or more caches (e.g., GPU caches 334) may be changed from being based on virtual address to being based on physical address or vice versa.

Yet another, non-limiting, example of a behavior modification would be to disable an I-cache pre-fetch function in the timing testing mode for one or more I-caches that have such a function enabled in the normal mode.

Configuring the hardware and performing operations as described above (e.g., configuring the CPU cores to run at different frequencies) may expose errors in synchronization logic, but if the real time behavior of the device is important, the timing testing mode itself may cause errors in operation, e.g., in the case of a video game console, errors due to the inability of the lower speed CPU cores to meet real time deadlines imposed by display timing, audio streamout or the like. According to aspects of the present disclosure, in timing testing mode, the device 300 may be run at higher than standard operating speed. By way of non-limiting example, the higher than standard operating speed may be about 5% to about 30% higher than the standard operating speed. By way of example, but not by way of limitation, in timing testing mode, the clock of the CPU, CPU caches, GPU, internal bus, and memory may be set to higher frequencies than the standard operating frequency (or the standard operating frequency range) of the device. As the mass produced version of the device 300 may be constructed in such a way as to preclude setting of clocks at above standard operating frequencies, specially designed hardware may need to be created, for example hardware that uses higher speed memory chips than a corresponding mass produced device, or uses the portion of a manufacturing run of a system on chip (SoC) that allows higher speed operation than average, or uses higher spec motherboards, power supplies, and cooling systems than are used on the mass produced device.
There are a number of ways in which application errors may be manifested in the timing testing mode. According to one implementation, the specially designed hardware may include a circuit or circuits configured to determine the number of instructions per cycle (IPC) executed by the device 300. The OS 321 may monitor changes in IPC to test for errors in the application. The OS may correlate significant variations in IPC to particular modifications to operation of the device in timing testing mode.
In other embodiments, CPU resources may be reduced when the device operates in the timing testing mode. Examples of such CPU resource reduction include, but are not limited to reducing the size of store queues, load queues, or caches (e.g., L1 or higher, I-cache, D-cache, ITLB, or DTLB). Other examples include, but are not limited to reducing the rate of execution of ALU, AGU, SIMD pipes, or specific instructions. In addition, one or more individual cores or application threads may be randomly or systematically preempted. Additional examples include delaying or speeding up or changing timing when using OS functionality, changing use of cores by the OS, altering virtual to physical core assignment (e.g., inter-cluster competition), leveraging other asymmetries, or writing back or invalidating caches and/or TLBs.
Examples of sending commands to hardware components in ways that disrupt timing at 544include altering the functioning of the memory 340 or memory controller 315. Examples of such alteration of memory or memory controller functioning include, but are not limited to, running a memory clock/ and internal bus clock different frequencies, inserting noise into memory operations, adding latency to memory operations, changing priorities of memory operations, and changing row and/or column channel bits, to simulate different channel counts or row breaks.
Jaguar has no L3.
In another example, a more powerful APU may contain a L3 cache for the CPU, compared to a less powerful APU that did not have such a cache.
In alternative implementations, the CPU 120 and GPU 130 may be implemented as separate hardware components on separate chips
For example, in the context of GPUs, parallel processing threads are bunched in what is sometimes called a "warp" (for NVIDIA hardware) or a "wavefront" (for AMD hardware) as the most basic unit of scheduling, the difference primarily being the number of threads that are grouped together.

IF call-out
To facilitate communication among the cores in a cluster, the clusters 201-1 . . . 202-M may include corresponding local busses 205-1 . . . 205-M coupled to each of the cores and the cluster-level cache for the cluster. Likewise, to facilitate communication among the clusters, the CPU 200 may include one or more higher-level busses 206 coupled to the clusters 201-1 . . . 201-M and to the higher level cache 204.

Jaguar has no HT/SMT:
Depending on the specifics of the CPU 200, a core may be capable of executing only one thread at once, or may be capable of executing multiple threads simultaneously ("hyperthreading"). In the case of a hyperthreaded CPU, an application may also designate which threads may be executed simultaneously with which other threads. Performance of a thread is impacted by the specific processing performed by any other threads being executed by the same core.
 
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BitsandBytes

Member
Dec 16, 2017
4,576
The language talks about altering cache behavior and outright disabling some features in the CPU. The GPU was architectural enhanced, but the CPU was just a faster Jaguar. They could downclock it and call it a day.

Either way it will be interesting how they go about it. I doubt we'll hear much detail above it is BC when the proper hype/leaks start so we could be in for a long wait to find out.
 

Deleted member 5764

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Oct 25, 2017
6,574
Thanks.

So if PS5 has 16GB of total RAM for OS + games and the OS demands more RAM than PS4 did and it should, let's say by an extra 2GB, then around 11GB would be free for games?

Is 11GB enough?

It's a jump that I don't think I'd complain about too much. Especially when we've seen what the PS4 Pro can give us with half that amount.
 

Rychu

Member
Oct 25, 2017
8,260
Utah, USA
No worries! I'm not sure we have any real leaks or rumors about the X018 event just yet. I've seen speculation but that's about it. Knowing Microsoft, I'm sure that something will get out prior to November though...
We don't have much. Jez Corden said he would "bet money" on seeing a streaming service from Microsoft, acquisitions and a blowout of Crackdown 3 info though.

He thinks it's pretty much guaranteed we will see game streaming or at least hear about it at X0. Maybe a demo showing off the game streaming streaming Gears 5 or something like that?
 

Deleted member 38397

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Jan 15, 2018
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I don't know if it's because of the weird filming angle and maybe only filming part of the screen but that Harry Potter game looks like it was played with a Wiimote or something. The cursor for the wand seemed to be independent of the camera controls.
 

Deleted member 36493

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Dec 19, 2017
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HP impressed me with the realtime ? destructions, that's something I expect from next gen titles.
Bear in mind this is an early footage so lot of times left before fall 2020.


HiRbrgw.gif
If this was real-time, then it has much better physics than any game today. This really doesn't look possible on current-gen consoles to me, it looks like the stuff you see in tech demos.
 

Benji

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Oct 25, 2017
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Potter is targeted towards next generation consoles specifically

Whether they end up making it cross gen I'm not sure. But the target is next gen
 

Deleted member 36493

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Dec 19, 2017
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Potter is targeted towards next generation consoles specifically

Whether they end up making it cross gen I'm not sure. But the target is next gen
That makes sense because it looks like the physics will be an actual gameplay mechanic and I'm not sure that's something that can "scale" well across generations.

In this gen, developers haven't been able to really use physics as a gameplay mechanic. It's usually just a small touch that enhances immersion. Batman's cape sways in the wind, Kratos' axe bounces as he moves etc.
 

Kyoufu

Member
Oct 26, 2017
16,582
Warner Bros have no problem downgrading games so they can run on last gen consoles (see Shadow of Mordor), so Harry Potter probably isn't next-gen only. I would be very surprised if any 3rd party publisher released next-gen exclusive AAA titles in 2020 tbh!
 

SteamyPunk

Member
Oct 26, 2017
463
If the HP game is targeting 2020 and next gen, wouldn't this point to next gen starting late 2019? They're not going to release a big licensed property game next gen-only at launch...right?
 

Deleted member 36493

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Dec 19, 2017
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Warner Bros have no problem downgrading games so they can run on last gen consoles (see Shadow of Mordor), so Harry Potter probably isn't next-gen only. I would be very surprised if any 3rd party publisher released next-gen exclusive AAA titles in 2020 tbh!
But if the extra power is being used for a gameplay mechanic (i.e. physics), how can it be downgraded without the mechanic being affected? Especially since the current consoles and next-gen consoles are expected to have a huge difference in processing power that allows for these mechanics to be implemented?
 

Gamer17

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Oct 30, 2017
9,399
If the HP game is targeting 2020 and next gen, wouldn't this point to next gen starting late 2019? They're not going to release a big licensed property game next gen-only at launch...right?
If they want spotlight , it's a great tactic to go the frist 2 months the console launches in holidays as they will enjoy a good few million sales as everyone will look pass the short comings due to lack of competition
 

Kyoufu

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Oct 26, 2017
16,582
But if the extra power is being used for a gameplay mechanic (i.e. physics), how can it be downgraded without the mechanic being affected? Especially since the current consoles and next-gen consoles are expected to have a huge difference in processing power that allows for these mechanics to be implemented?

Like I said, if they have to drop something in the porting process then they will.

Here's a quote from the Shadow of Mordor devs:

"We're very focused on the PS4 and Xbox One," he said. "We're focusing on the next-gen platforms, and then going to do whatever we can to get as much as possible on current-gen."

http://uk.ign.com/articles/2014/02/20/middle-earth-shadow-of-mordor-focused-on-ps4-and-xbox-one

Sure, the best experience will be on next-gen consoles, but it doesn't mean it'll be the only place to experience the game. Nobody is going to spend millions and millions on a AAA open world RPG or whatever the Harry Potter game is and make it next-gen only. That just makes no business sense in 2020. Warner Bros must have high expectations for this project, so... good luck to anyone expecting next-gen only imo!
 

Benji

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Oct 25, 2017
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Your going to see publishers embrace next generation in a much more aggressive manner than you saw the transition to this generation.

Believe it or not a lot of the decision makers in the industry were actually buying into the idea consoles were doomed and everyone would either be on PC or mobile. There isnt the same sort of trepidation this time around and next gen wont be starting near as slowly as this one did, as projects are being green lit much earlier this time around.
 

Gamer17

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Oct 30, 2017
9,399
Your going to see publishers embrace next generation in a much more aggressive manner than you saw the transition to this generation.

Believe it or not a lot of the decision makers in the industry were actually buying into the idea consoles were doomed and everyone would either be on PC or mobile. There isnt the same sort of trepidation this time around and next gen wont be starting near as slowly as this one did, as projects are being green lit much earlier this time around.
Thats a good point . Thanks for clarifying it.
 

TiG

Avenger
Oct 25, 2017
809
Your going to see publishers embrace next generation in a much more aggressive manner than you saw the transition to this generation.

Believe it or not a lot of the decision makers in the industry were actually buying into the idea consoles were doomed and everyone would either be on PC or mobile. There isnt the same sort of trepidation this time around and next gen wont be starting near as slowly as this one did, as projects are being green lit much earlier this time around.

This is making me very excited. Seeing the whole industry going guns blazing will be awesome!

Btw, thank you Benji for the various tidbits you've been giving us!
 

2Blackcats

Member
Oct 26, 2017
16,053
Your going to see publishers embrace next generation in a much more aggressive manner than you saw the transition to this generation.

Believe it or not a lot of the decision makers in the industry were actually buying into the idea consoles were doomed and everyone would either be on PC or mobile. There isnt the same sort of trepidation this time around and next gen wont be starting near as slowly as this one did, as projects are being green lit much earlier this time around.

Fantastic news, thanks.
 

TiG

Avenger
Oct 25, 2017
809
I think PS5 will be Early 2020 and Xbox will be late 2020. However, Microsoft might launch their streaming console earlier (mid 2020?).

I think Sony might just announced the PS5 at PSX 2019?
 
Jan 2, 2018
2,027
Your going to see publishers embrace next generation in a much more aggressive manner than you saw the transition to this generation.

Believe it or not a lot of the decision makers in the industry were actually buying into the idea consoles were doomed and everyone would either be on PC or mobile. There isnt the same sort of trepidation this time around and next gen wont be starting near as slowly as this one did, as projects are being green lit much earlier this time around.
This makes me so happy, I remember how in 2012 there was this feeling that this was it,gaming is going full mobile/F2P.
Would you say that influenced both Sony/MS at the time when it came to console hardware? that console gaming was done? did both of them tried to push only the bare minimum of what they thought would be consider a new gen? It looks like that won't be the case this time,hopefully.
I really hope this gen's success would convince both to push with the specs.
 

Gamer17

Banned
Oct 30, 2017
9,399
In that window I should clarify.

I'm not saying the game will be available day 1 on next generation. But yeah that time frame
So rumors of Sony pushing back ps5 to 2020 is true .do u know why they pushed it back ?sales of ps4 or games not being ready or 7nm isn't ready or...??
 

Thorrgal

Member
Oct 26, 2017
12,291
That's just my personal speculation, but I think it makes sense. I can see Microsoft treating the Scarlett devices as a clean slate in terms of retail presence, all while still supporting the "One" family of devices for their streaming service.

I don't think Microsoft would be designing a budget-minded, streaming-focused box if they intended on keeping the One S around long term.

It's the first explanation for forward compatibility that I read that makes sense. Well done