EDIT: Regarding RAM, it doesn't mention a change in the RAM type or amount but would the RAM bus width depend on the CPU board, which is being changed? Or would they have to specifically mention that too?
Bandwidth would depend mainly on the SoC and the RAM chips themselves (and only the board if you actually increase the bus width). The current SoC has a 64bit memory interface clocked at 1600Mhz and it's connected to two memory chips with a 32bit interface each. There's two ways to increase memory bandwith there and, given what is in the FCC application, both seem unlikely:
- You use faster RAM, but the FCC application doesn't mention the revision to use different RAM (also, I'm also not sure whether it's actually possible to go higher than 1600Mhz with LPDDR4).
- You use a wider (128bit) memory interface, but this would, again, require different memory chips with a 64bit interface each and the FCC application doesn't mention anything like this.