Thanks for the link
anexanhume.
So with HBM we would be looking at significantly higher bandwidth with a lower power draw? The only downside being cost of course.
Isn't memory bandwidth the reason that titles like Uncharted 4 couldn't reach higher than 1440p or even checkerboard because of the deferred rendering it used?
HBM is only higher bandwidth if they use enough stacks or somehow get HBM3 in there. Otherwise, GDDR6 can beat up to 3 stacks with a 384 bit interface.
That patent is potentially exciting.
So it might be for some type of 2.5D or 3D stacking, be it processor stacking and/or memory stacking (ala HBM) within a chip package, correct?
Yes. Or they could even stack chiplets if they had TSVs. That's pretty advanced, though.
So this is interesting, but does this picture look familiar?
Now obvsiouly Sony is not working with intel, just thought it interesting. This pic is from an article released hours ago.
https://www.top500.org/news/intel-goes-vertical-will-stack-logic-chips-into-3d-packages/
That's 2.5D stacking. To be fair, it's kind of a gray area given that's an active interposer, but the logic die themselves don't have TSV, which is the traditional threshold for '3D' stacking. The patent image shows potential 3D stacking.
I wouldn't think so.
The transistors are where heat is generated. Placing a cooler on the mobo underneath would be placing an additional barrier of thermal resistance between the heat source and the heat sink. You want your heat sink mounted directly on the chip packages, to pull away as much heat as possible and keep those cores running efficiently.
There would not solely be a motherboard interface. The image shows some kind of metal interface on the top of the PWB, which interfaces to through-hole metal posts, which then interface to a true heatsink on the opposing side of the PWB. You'd be more thermally limited than a conventional heatsink (not all of it could be air-cooled, you create a non-ideal metal interface, etc.)
However, you could potentially mount your die upside down on the underside of the package, still allowing for direct die contact with your thermal interface. In fact, I think this is exactly what is depicted with 5a. Then, you could stack your memory or other chiplet device on the other side of the package. This way, you achieve a 3D-like solution without the need for any TSVs potentially (depending on the density of interconnects achieved in the package). Your chips certainly wouldn't need TSVs at least, unless they are stacked on themselves like HBM.
Additionally, some packaging technologies allow for embedded active components. Again, this is another exotic, probably more far-out technology, but if the dissipation is low enough, one could certainly do it.
Xbox uses GDDR5 on a 384-bit bus.
A question though: How would MS fair with backwards compatibility in regards to using a 256-bit bus with GDDR6? Or am I complicating things and the only thing that actually matters is raw bandwidth numbers?
Only bandwidth matters. The memory controller is going to abstract the particularizes when it comes to how the CPU and GPU get their bandwidth. GDDR6 is actually more granular than GDDR5, so there's no worries there.