There's been a lot of back and forth regarding rumors, so here's a rough timeline from memory. Feel free to correct me if I get the order wrong.
2018:
- At some point, it begins to be rumored that PS5, originally slated for 2019, will hit 2020. Backwards compatibility is cited as one potential cause.
- Late 2018 - it's rumored that Navi had some design issues and needed a design spin. Supposedly what comes to be known as Navi 10 is not actually the first chip design.
2019:
- Early 2019 - AMD gets Navi design spin back and validates it for release in summer.
- First rumors of PS5 devkits appear. Most claim some sort of APU.
- Wired article appears, with timing suspected because dev kits have started to filter out. It confirms BC with PS4.
- Mid 2019 - Navi 10 finally launches, and the configuration matches the GPUs seen in PS5 dev kit configurations.
- Further Wired article confirms that PS5 RT is indeed hardware based, echoing what forum insiders had already said. Others have claimed VRS is also included. To date, no driver or repo leak has indicated either feature in any PS5 GPU configuration. Most importantly, the GPU hardware wouldn't need RT or VRS hardware to do the BC testing Sony is asking for, nor would it need more than 36 CUs.
- Late 2019 - Navi 12/14 leaks reveal smaller and different memory configured parts. Likelihood these preceded the "real" Navi 10 design diminish.
- Sony reveals that while aiming for total BC compatibility, they may not reach that goal. This perhaps suggests there is some credence to BC being an issue with the console's development.
- Navi 21 also shows up as the first Navi iteration with RT and VRS hardware.
- Examination of github repos reveals Ariel/Oberon BC testing and the existence of Arden with RT/VRS and 56 CUs, suggesting a later RDNA version.
As it stands now, the ambiguity of the extensiveness of this testing, and the confirmation of VRS/RT in Arden despite it containing less info about that hardware overall are the things causing the most confusion and debate about the PS5's final GPU configuration and whether we have seen it yet.
I'll also point out that Sony's SN Systems work on scheduler models and machine code analyzers (MCA) shows they're trying to have some capability of BC testing without needing physical hardware to find what edge cases may break BC. AMD added
Zen 2 scheduler modeling in August of last year.
Ariel and Oberon as conceived need not be completely custom hardware, either. It's possible they could use off-the-shelf Zen 2 and Navi 10 die with only a custom IO die with some glue logic built on GloFo's robust 12nm process. This gives them more reflective hardware to play with well ahead of launch and when they'd normally have test silicon to exercise.
Personally, I think there is value in a non-final version of the APU for developers to have access to and for Sony to iron out their BC solution if they think it is key to quick platform adoption. Indeed, early feedback from developers and Sony's own words indicate the PS5 is extremely developer friendly.
A key question will be whether or not the APU got a design spin to incorporate RT or VRS as a result of Navi's initial delay or Sony's protracted timeline to get BC working. We may never know the answer to that. Knowing they couldn't launch in 2019 meant a whole extra year of development time, and some of AMD's planned RDNA 2.0 features may have become possible then. Having earlier Navi versions to use would have been risk reduction even if the inclusion of said features presented a challenging timeline for a 2020 launch. There's also a bit of keeping up with the Joneses here. They had to know that if they were launching in 2020, Microsoft would have those features. Not having RT when your competitor does would have been quite the marketing challenge.
Of course, none of this is reflective and what total number of CUs or clock speeds even further revision might have. However, the target 2.0GHz clock frequency of the dev kit indicates they had some intent for it beyond simple BC testing. It's not realistic to expect a higher clock than that, so it's difficult to discern whether that 9.2TF is what they expected out of final hardware, or it was simply the best they could do with released silicon at the time.
