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Next-gen PS5 and next Xbox speculation launch thread |OT5| - It's in RDNA
- Thread starter Mecha Meister
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Spencer actually said they were working to get dev-kits out, but gave no indication they hadn't started yet.
I only saw this narrative of Scarlet dev-kits not being available after the Reiner tweets.
I'm not saying it doesn't exist or it didn't exist at some point.
Yes. One possibility - Zen 2 + Navi 10 is the devkit with monolithic APU to come. They could even have a common package pinout.
Fair enough, but you asked for evidence it existed, and that's what we got.
There's no reason to believe it's not happening
It has that dope cooling system. It has no power brick. And it's smaller than ever. It's unbelievable
Nice illustration. I think a consequence of the stratified cache structure will be more granular flexibility in organization as you illustrate here.Some more into how did I land with stream processors in my most recent prediction after E3:
With the new RDNA architecture the old ways to design the GPU wasn't anymore. Less and wider Shader Engines. So I asked myself in what steps you could actually expand the number of CUs without producing gaps in die space that potentially would end up as dark silicon.
My result is shown with the below picture.
Setup A shows a possible design with up to 22 WGPs (48 CUs) but as usually I assume 1 WGP deactived per SE for yield purposes. This is a valid setup but I expect both platform holders will go for more.
The result was the next possible step in expanding the GPU: Setup B.
Btw, the inactive WGPs (IA) were picked randomly.
One cool thing about the Tom's Hardware article about the Navi TDPs is that we have now very trustworthy and well-defined metrics for 14gbps GGDR6 modules (2W per module) and what they consider the average VRM efficiency (85%-ish).
No I didn't. I asked for evidence that that poster's hints that the leaks about two SKUs were in fact controlled and deliberate reveals by MS.
You know, as a first iteration of a new console i wonder if Anaconda will forgo the Scorpios refinement. Will the new system be loud, not use vaporcooling? Have a powerbrick? Be big?
yes, it doesnt make much sense when you compare it to whats been revealed so far.
but im just looking at the estimated die size of the Scarlett and its definitely bigger than the Navi 10 chip even after the 70mm2 CPU. 5700XT is 251mm2 with 70mm2, you are looking at a 321mm2 chip if they go with the RX5700XT chip. the estimates put the scarlet chip at 390-400mm2. so there is roughly 80mm2. lots of space for 35% more CUs and RT hardware. maybe they go with 54 CUs at 1.2 ghz but thats still an 8.2 tflops. so at that point, why go with a bigger chip?
So yeah, i am completely ignoring the RX5700 cards right now. they dont make much sense. their tdp and tbp is way too high for 7nm cards with just 40 CUs. Shader processors havent increased either and all their architectural improvements have only netted them 25% more performance. to me, thats the shittiest gains ever and almost gives Adoredtv credibility. the 5700XT is a 9.4 tflops GPU. its tdp is 150w. i believe this includes the 8gb of ram. we know the CPU will be around 40w. then you've got all the other stuff on the mobo including the other 16 gb of ram, uhd and well everything else. best case scenario, we are looking at a 225w console. so how does one take the 5700xt, put it in a console and then increase the clocks to hit 10 tflops like most here expect?
the answer is you cant. AMD is already using the clocks at 1.9ghz to get to the 9.4 tflops. if next gen consoles have 40 CUs, how do we get to 10 tflops? how can next gen consoles have 40 CUs? surely they will have to disable 4. so are we seriously back to 36 CU and 8 tflops?
we have to start thinking bigger and ignore these shitty gpus altogether.
Could it be that no actual dev kits had gone out for MS yet but instead they gave specs to devs making games for next gen to target? And if at that point they were still looking at a 2 sku approach would that initial target be the lower spec to machine? I mean that would play into the narrative we heard about the playstation 5 dev kit being decidedly more powerful then Scarlet at that point. Just my tin foil hat on...
You're not giving MS enough credit here. It was more than vapor chamber cooling that allowed them to clock that high. You're disregarding the degree that the Hovis Method mattered.
It's not right to trivialize what the Xbox hardware team achieved with Xbox One X by saying they just bolted on a vapor chamber cooler and threw money at the problem.
Rich had a AMD meeting of some sort where he got some Zen/Navi info (I wouldn't expect anything major from this but still). He also supposedly had some "interesting" PS5 info. They were supposed to be making a vid about it. It could just have been delayed but yeah.
I know that this illustration is not precise. But it was the best available to me.
Actually I followed your idea with the 3 Shader Engines too but in result it took 8 blocks for just adding 1 active WGP (see below).
I did not show that but I have now updated the diagram with that setup too and the number of tiles for each setup.
With the die size estimate we have for Scarlett, I don't see why we can't expect 44-48 CUs and >10TF. Based on in-game performance of the 5700 being ~Vega 64 level, my current expectation for both next gen consoles is around Radeon 7 levels of performance. 🤷♂️
So... We have ignore the concrete data and real world products ?
You say these are shitty gpus. But they're doing what reasonable expectations were thinking: Matching VEGA64 at a lower CU count and TDP and higher IPC.
Also, not every console gpus have disabled CU. I dont recall the One X having disabled CUs for exemple (I might be wrong here though).
From now on, this is wishful thinking.
You have to stay in line with current existing products, otherwise this is pure fantasy.
Thanks. Some interesting info in that article after giving it a quick scan. Explains that German TDP/TBP chart that's been floating around.
We can say 24 Gb of GGDR6 will consume at least 48 watts probably more because of the larger bus 384 bits.
Has there been any source that mentioned Lockhart being canceled that wasn't pure speculation? The lack of announcement isn't enough to go on when all of the things they announced (CPU, type of RAM, SSD) are common to all Scarlett devices and the things they didn't are where they vary.
With the lack of hard information in the announcement I have a hard time reading into anything too much. If anything, them avoiding questions about multiple consoles supports that existence of Lockhart not the other way around.
With the lack of hard information in the announcement I have a hard time reading into anything too much. If anything, them avoiding questions about multiple consoles supports that existence of Lockhart not the other way around.
I bet you could get 8 Zen 2 cores down to 30W while running at a reasonably high frequency of like let's say 3GHz.
X570 is confirmed to be the 14nm version of the IO die of Matisse and it has a TDP of 11-14W. While the IO die is 12nm, it does have an active DDR4 controller and it spits out 24 PCIe lanes instead of 16-20. At that point you can assume that the IO die uses about 20-25W, so the actual 8C chiplet of a 3700X will probably have a TDP of around 40-45W which runs at 3.6GHz base and 4.4GHz boost. If you let it run at a fixed clock with a lower voltage and throw in a potentially smaller node like 6nm, 7nm+ or Samsung's 7nm, you're definitely going to end up lower than 40W for the CPU.
Obviously that's just a guess as for now we don't know yet what the real power numbers are until someone does some testing.
I don't think power consumption scales linearly with density, though - so, if they're using 12x 16Gb modules instead of 24x 8Gb, for instance, I'm not completely sure you'll get twice as much power usage. 48W is probably the ceiling, 24W the floor, truth being somewhere between.
xbox one x had 4 disabled cus.
Fine, lets not ignore these gpus. lets go with concrete data and real world products. these gpus dont have hardware RT. no hardware RT in Scarlet confirmed. Phil was lying. it's the only explanation.
What we do know is that a 384-bit Scarlet (if it's 384-bit and not 320-bit, the video was hard to follow) with 24GB of GDDR6 will consume less than the X memory configuration.
Power consumption of DDR4 is linear per module, I doubt this is different for GGDR6, the same thing for HBM2 8 Gb of HBM2 consume 10 watts, 16 Gb consumes 20 watts
Radeon 7 is already a 7nm card and the architectural advantages of Navi don't make up the gap enough to replicate that kind of performance in a console which is bound by certain thermal restrictions. The Radeon 7 also has HMB2 memory which Navi doesn't have.
That's how semi-custom works. You can add stuff on top of it. And the next one are going to have it. Which also means you know now how you're getting a bigger chip.
I think the Xbox One X having inside a GPU nearly equal to a desktop 185 watts TDP Polaris GPU, I think the 11,1 Tflops rumor is much more reasonable now.
Oh right I see, some other sources said the gpu power draw was 180w + 150w
But your source does look more detailed.
Colbert's thoughts about NAVI GPU setups for next gen consoles
💬 NAVI GPU layouts analyzed 💬
Some more info how did I land with number of stream processors in my most recent prediction after E3:
With the new RDNA architecture the old ways to design the GPU wasn't anymore. Less and wider Shader Engines. So I asked myself in what steps you could actually expand the number of CUs without producing gaps in die space that potentially would end up as dark silicon.
My results are shown with the below picture after the wall of text ;)
Setup A shows a possible design with up to 22 WGPs (48 CUs) but as usual I assume 1 WGP deactived per SE for yield purposes (NA).
Setup B is the next iteration of expanding on WGPs (and CUs).
With Setup C I also followed the idea of anexanhume with 3 shader engines but rejected it because it comes with a lot of tiles for just 1 WGP.
If we assume each block consumes the same die space (which I know is not the case but just as an approximation) we get the following results:
Btw, the inactive WGPs (NA) were picked randomly.
Some more info how did I land with number of stream processors in my most recent prediction after E3:
With the new RDNA architecture the old ways to design the GPU wasn't anymore. Less and wider Shader Engines. So I asked myself in what steps you could actually expand the number of CUs without producing gaps in die space that potentially would end up as dark silicon.
My results are shown with the below picture after the wall of text ;)
Setup A shows a possible design with up to 22 WGPs (48 CUs) but as usual I assume 1 WGP deactived per SE for yield purposes (NA).
Setup B is the next iteration of expanding on WGPs (and CUs).
With Setup C I also followed the idea of anexanhume with 3 shader engines but rejected it because it comes with a lot of tiles for just 1 WGP.
If we assume each block consumes the same die space (which I know is not the case but just as an approximation) we get the following results:
- Setup A adds 12.5 % tile space for additional 4 active CUs
- Setup B adds 25.0 % tile space for additional 12 active CUs
- Setup C adds 50.0 % tile space for additional 14 active CUs
Btw, the inactive WGPs (NA) were picked randomly.
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As far as I know, DRAM power consumption scales with the number of modules. So 12GB on a 382-bit interface will consume the same as a 24GB on a 382-bit interface. So if the X has a 382-bit interface, Scarlet will consume less power with a 382-bit interface because GDDR6 consume less power than GDDR5 while providing x2 the bandwidth. If the X uses 12GB of 6.8Gbps GDDR5 in a 382-bit interface, Scarlet can use 24GB of 13.6Gbps GDDR6 in a 382-bit interface (650GB/s) and consume ~15% less than the X.
Are you considering the die area hardware RT is going to consume? Is anyone?
So what's your prediction based on the new gpus? Especially with ms custom hardware rt?
That desktop card was a 185 w card by the same measure by which the 5700 is a 180 w card.
Yeah, but compared to the 225W 5700 XT you are talking about 15% more TF + RT hardware + more memory controllers + all the Microsoft/Sony customization. Sounds a bit too good to be true.
I stand by what I said before: 12-13TFLOPs of GCN metric. That means VEGA64 level of performance, +/-10% around that. RX5700 XT fits the bill. Put in RT cores and call it a day. I wonder if they could use CU's for RT, but I'm doubtful.
But as of right now, RX5700 XT fits the bill in both performance level and power consumption level. You people are too focused on CU numbers and TFLOPs from an older architecture.
What is IA on your setup A, B and C ? I really hope you don't expect AMD to design a GPU with unused space ? And Setup C is not happening. I think the SEs need to be grouped in the center.💬 NAVI GPU setups analyzed 💬
Some more info how did I land with number of stream processors in my most recent prediction after E3:
With the new RDNA architecture the old ways to design the GPU wasn't anymore. Less and wider Shader Engines. So I asked myself in what steps you could actually expand the number of CUs without producing gaps in die space that potentially would end up as dark silicon.
My results are shown with the below picture after the wall of text ;)
Setup A shows a possible design with up to 22 WGPs (48 CUs) but as usual I assume 1 WGP deactived per SE for yield purposes.
Setup B is the next iteration of expanding on WGPs (and CUs).
With Setup C I also followed the idea of anexanhume with 3 shader engines but rejected it because it comes with a lot of tiles for just 1 WGP.
If we assume each block consumes the same die space (which I know is not the case but just as an approximation) we get the following results:
So looking into the numbers I had to go with Setup B as it gives you the most bang for the buck! (CU/tile space increase ratio)!!
- Setup A adds 12.5 % tile space for additional 4 active CUs
- Setup B adds 25.0 % tile space for additional 12 active CUs
- Setup C adds 50.0 % tile space for additional 14 active CUs
Btw, the inactive WGPs (IA) were picked randomly.
EDIT: OK, IA means deactivated CU.
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